1. Field of the invention
The invention relates not only to a processor that includes the function of concurrently executing a plurality of instructions by means of pipeline control or the like and an interrupt function, but also to an interrupt control method adapted for such processor.
2. Related art
Various types of processors such as pipeline processors that are capable of concurrently executing a plurality of instructions are known. According to these types of processors, instructions can be executed sequentially within a duration shorter than that required for executing the instructions on an individual basis. Therefore, the time required for executing the whole program can be reduced.
FIG. 3 shows an exemplary program prepared for such a type of processor capable of concurrently executing a plurality of instructions. Respective instructions constituting a program are sequentially executed by the processor in synchronism with a clock that is generated at a predetermined frequency. Further, the processor starts executing a succeeding instruction without waiting for the termination of a preceding instruction when these instructions are executed sequentially.
For example, the program has, on a third line from the head thereof, an instruction that reads: "Func1 R4, R0, R1". This instruction instructs the processor to "execute an operation "Func1" upon data stored in registers R0 and R1 and store the result in register R4", and requires three (3) clocks from the start to the end of the execution. Other instructions "Func1 . . . " are similar. The duration required for the execution of an instruction is indicated by an arrow per instruction in FIG. 3.
The processor starts executing the instruction on third line and then starts executing an instruction on fourth line "Func1 R5, R2, R3" without waiting for the termination of the instruction on third line. That is, the processor concurrently executes the instructions on third and fourth lines. The processor thereafter starts executing succeeding instructions sequentially every time a clock is generated.
Immediately before an instruction on sixth line from the head, "Func1 R5, R4, R8", is started, the instruction on third line is terminated, and the result of the operation Func1 is stored in register R4. Therefore, during the execution of the instruction on sixth line, the data stored in register R4 by the execution of the instruction on third line is referred to.
By the way, before starting to execute the instruction on sixth line, an instruction on fifth line, "Func1 R4, R6, R7", is started. The content of register R4 would be updated upon end of the instruction on fifth line.
However, the instruction on fifth line will not be terminated by the time the instruction on sixth line is started. Therefore, during the execution of the instruction on sixth line, it is the data stored in register R4 by the execution of the instruction on third line, not the result obtained by the execution of the instruction on fifth line, that is referred to as described above.
Then, upon end of a series of instructions "Func1 . . . ", three (3) instructions, "STA(R9+), R5", are executed. Each of these instructions instructs the processor to "add the content of register R5 to data in register R9 and store the sum in register R9". Further, the last instruction of the program is "JNE R9, R11, Top". This instruction instructs the processor to "jump to a line labeled "Top" when the content of register R9 does not coincide with the content of register R11. That is, this program is so looped as to repeat instructions from a line labeled "Top" to the last line until a predetermined condition prevails.
As described above, the processor capable of concurrently executing a plurality of instructions can start executing a succeeding instruction without waiting for the end of execution of a preceding instruction. Therefore, the execution time for the whole program can be reduced.
When a plurality of instructions are to be executed concurrently as described above, each instruction constituting the program must be executed at a predetermined timing so that the program can be executed regularly. However, in order to make the system flexible, the system must be designed so that interrupt requests are accepted to some degree, unless such system is designed to be dedicated to executing only a single type of program. The following methods have heretofore been proposed to meet this system design requirement.
(1) First Method
The first method is characterized as interposing a group of instructions between an instruction that specifies interrupt prohibit and an instruction that specifies interrupt prohibit reset so that a processor can respond to an interrupt request in accordance with these instructions. The group of instructions are in a program and their execution timings must not be changed. The program shown in FIG. 3 is designed so that interrupt control is implemented by this method. That is, the program has instructions "Disable" and "Enable". The former specifies interrupt prohibit and the latter specifies interrupt prohibit reset. No interrupt request is accepted at all during an interval between the start of the Disable instruction and the start of the Enable instruction.
(2) Second Method
The second method is characterized in that when an interrupt request occurs upon starting of an instruction, the processor is caused to execute an interrupt process while accepting the interrupt request, and the processor retroactively executes again all the past instructions having been concurrently executed together with the instruction being interrupted by the interrupt process.
(3) Third Method
The third method is characterized as giving priority to flexible acceptance of interrupt requests and giving up concurrent execution of a plurality of instructions. That is, the processor does not execute a succeeding instruction until a preceding instruction is terminated.
The first to third methods described above have the following shortcomings. First, as in the exemplary program shown in FIG. 3, if an interrupt prohibit instruction (Disable instruction) and an interrupt prohibit reset instruction (Enable instruction) are included in a loop process, the first method requires overhead operations for executing these instructions every time the loop makes one complete execution, and this impairs execution efficiency. Further, if there are many instructions that require a large number of predetermined clocks (i.e., instructions requiring a long execution time) in a group of instructions to be concurrently executed, the second method addresses the shortcoming that the execution is interrupted by an interrupt request at a high probability, which in turn increases the probability of executing the group of instructions again as a result of the interrupt process. Further, the third method has the shortcoming that the execution efficiency is low because concurrent execution is not executed.